Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Many modern computing systems utilize multi-core processors having two or more cores interfaced for enhanced performance and efficient processing of multiple tasks and threads. Data required for execution of single and multiple thread applications may be stored across caches of multiple cores of the multi-core processors, where the cores used for storing data may be different from those cores used for executing the single or multiple threads. During operation, such data may be accessed from the cached locations across multiple cores and the cached locations of memory addresses may need to be determined.
Cache coherence protocols implemented for multi-core processors may incorporate functionalities to determine cached locations of the memory addresses. For example, centralized directories may be utilized to determine cached location of a given memory address. In certain multi-core processors, distributed directories may be implemented where look-up requests for one or more memory addresses may be sent to the directories and subsequently the directories are searched for the memory addresses. In other multi-core processors, core level directories may be utilized for determination of location of certain memory addresses.